The VHDL-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.
[1] VHDL-AMS is an industry standard modeling language for mixed signal circuits.
It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits.
It is particularly well suited for verification of very complex analog, mixed-signal and radio frequency integrated circuits.
In VHDL-AMS, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation.