VHDL (VHSIC Hardware Description Language) is a hardware description language that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes.

To model analog and mixed-signal systems, an IEEE-standardized HDL based on VHDL called VHDL-AMS (officially IEEE 1076.1) has been developed.

In 1983, VHDL was originally developed at the behest of the U.S. Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment.

The next step was the development of logic synthesis tools that read the VHDL and output a definition of the physical implementation of the circuit.

The initial version of VHDL, designed to IEEE standard IEEE 1076–1987,[3] included a wide range of data types, including numerical (integer and real), logical (bit and Boolean), character and time, plus arrays of bit called bit_vector and of character called string.

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered.

Being a resolved subtype of its std_Ulogic parent type, std_logic-typed signals allow multiple driving for modeling bus structures, whereby the connected resolution function handles conflicting assignments adequately.

[specify] Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules.

IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors.

In June 2006, the VHDL Technical Committee of Accellera (delegated by IEEE to work on the next update of the standard) approved so-called Draft 3.0 of VHDL-2006.

While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier.

Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of case and generate statements, incorporation of VHPI (VHDL Procedural Interface) (interface to C/C++ languages) and a subset of PSL (Property Specification Language).

The language has undergone numerous revisions and has a variety of sub-standards associated with it that augment or extend it in important ways.

In this case, it might be possible to use VHDL to write a testbench to verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected.

It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical.

[16] In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation.

A simple AND gate in VHDL would look something like (Notice that RTL stands for Register transfer level design.)

However, more experienced designers usually avoid these compact forms and use a more verbose coding style for the sake of readability and maintainability.

It is generally considered a "best practice" to write very idiomatic code for synthesis as results can be incorrect or suboptimal for non-standard constructs.

[17] A more complex example of a MUX with 4x3 inputs and a 2-bit selector: A transparent latch is basically one bit of memory which is updated when an enable signal is raised.

Such waveform can be used, for example, as test vectors for a complex design or as a prototype of some synthesizer logic that will be implemented in the future.