It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits.
As such, they provide sophisticated and powerful language features for definition and synchronization of parallel actions and events.
On the other hand, many actions defined in HDL program statements can run in parallel (somewhat similar to threads and tasklets in procedural languages, but much more fine-grained).
The original intention of the Verilog-AMS committee was a single language for both analog and digital design, however due to delays in the merger process it remains at Accellera while Verilog evolved into SystemVerilog and went to the IEEE.
The following code example in Verilog-AMS shows a DAC which is an example for analog processing which is triggered by a digital signal: The ADC model is reading analog signals in the digital blocks: While the language was initially only supported by commercial companies, parts of the behavioural modeling subset, "Verilog-A" was adopted by the transistor-modeling community.