The Western Design Center (WDC) 65C02 microprocessor is an enhanced CMOS version of the popular nMOS-based 8-bit MOS Technology 6502.

Rockwell's primary interest was in the embedded market and asked for several new commands to be added to aid in this role.

Later versions were produced in PLCC and QFP packages, as well as PDIP, and with much higher clock speed ratings.

The current version from WDC, the W65C02S-14 has a fully static core and officially runs at speeds up to 14 MHz when powered at 5 volts.

[1] A Verilog hardware description model is available for designing the W65C02S core into an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

[7] Typical microprocessors not implemented in CMOS have dynamic cores and will lose their internal register contents (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values.

This information may be an artifact of an earlier data sheet, as a graph indicates that typical devices are capable of operation at higher speeds than suggested by the AC characteristics table, and that reliable operation at 20 MHz should be readily attainable with VDD at 5 volts, assuming the supporting hardware will allow it.

Designer Bill Mensch has pointed out that FMAX is affected by off-chip factors, such as the capacitive load on the microprocessor's pins.

Minimizing load by using short signal tracks and fewest devices helps raise FMAX.

[citation needed] Although the 65C02 can mostly be thought of as a low-power 6502, it also fixes several bugs found in the original and adds new instructions, addressing modes and features that can assist the programmer in writing smaller and faster-executing programs.

It is estimated that the average 6502 assembly language program can be made 10 to 15 percent smaller on the 65C02 and see a similar improvement in performance, largely through avoided memory accesses through the use of fewer instructions to accomplish a given task.

This was a deliberate design choice by MOS Technology, as it was deemed that implementing ROR was too costly in chip area for the benefits it provided.

The flaw, which some consider a bug, appears when the vector address ends in $FF, which is the boundary of a memory page.

Another by-design weakness that was revised by popular demand, the state of the (D)ecimal flag in the NMOS 6502's status register is undefined after a reset or interrupt.

This means programmers have to set the flag to a known value in order to avoid random errors caused by arithmetic operations performed in the mode other than the one intended, constititing software bugs.

As a result, one finds a CLD instruction (CLear Decimal) in almost all 6502 interrupt handlers, as well as early in the reset code.

During decimal mode arithmetic, the NMOS 6502 will put the (N)egative, o(V)erflow and (Z)ero flags into officially undefined states.

The 65C02 fixed this problem by performing a dummy read of the instruction opcode when indexing crosses a page boundary.

One common use for indirect addressing is to build branch tables, a list of entry points for subroutines that can be accessed using an index.

For instance, a device driver might list the entry points for OPEN, CLOSE, READ, etc in a table at $A000.

The new instructions were available from the start in Rockwell's R65C00 family,[19] but were not part of the original 65C02 specification and not found in versions made by WDC or its other licensees.

[16] In addition to the new commands above, WDC also added the STP and WAI instructions for supporting low-power modes.

WAIt has a similar effect, halting all processing, but this instruction resumes normal execution on the reception of an interrupt.

In the spinning case, the interrupt might arrive in the middle of one of the loop's instructions, and to allow it to restart after returning from the handler, the processor spends three cycles to save its location.