According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.
[1] As such, 2 nm is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous 3 nm node generation.
[25][26][needs update] In May 2021, IBM announced it had produced chips with 2 nm-class GAAFET transistors using three silicon layer nanosheets with a gate length of 12 nm.
The company confirmed their 2 nm process node called "Intel 20A",[notes 1] with "A" referring to an angstrom, a unit equivalent to 0.1 nanometers.
[34][needs update] In August 2022, a consortium of Japanese companies funded a new venture with government support called Rapidus for manufacturing of 2 nm chips.
Intel noted that they'd successfully implemented RibbonFET gate-all-around architecture and PowerVia backside power delivery in their 20A process, accelerating 18A development.
[48] In December 2021, Vertical-Transport FET (VTFET) CMOS logic transistor design with a vertical nanosheet was demonstrated at sub-45 nm gate pitch.
[50] Apart from the expected shrinking of transistor structures and interconnects, innovations forecasted by imec were as follows:[needs update] In September 2022, Samsung presented their future business goals, which at that time included an aim to mass-produce 1.4 nm by 2027.