[1] Discussion of analog verification began in 2005 when it started to become recognized that the analog portion of large mixed-signal chips had become so complex that a significant and ever-increasing number of these chips were being designed with functional errors in the analog portion that prevented them from operating correctly.
Applying a comprehensive testbench to an entire analog functional unit such as an audio codec, power Management IC, Power Management Unit, serdes, or RF transceiver, represented at the transistor level, is impractical.
One first builds simple models and tests benches for individual blocks.
Then testbenches are built for the entire analog functional unit and applied to the top-level schematic of that unit with the blocks represented with their now verified models.
To further improve the tests, one can perform mixed-level simulation, where the testbench for the functional unit is applied with one or two blocks at the transistor level, and all others at the model level.