Asynchronous array of simple processors

AsAP was developed by researchers in the VLSI Computation Laboratory (VCL) at the University of California, Davis and achieves high performance and energy efficiency, while using a relatively small circuit area.

[1] AsAP processors are well suited for implementation in future fabrication technologies, and are clocked in a globally asynchronous locally synchronous (GALS) fashion.

AsAP uses several novel key features, of which four are: A chip containing 36 (6x6) programmable processors was taped-out in May 2005 in 0.18 μm CMOS using a synthesized standard cell technology and is fully functional.

This operating point enables 1 trillion MAC or arithmetic logic unit (ALU) ops/sec with a power dissipation of only 9.2 watts.

Mapped tasks include: filters, convolutional coders, interleavers, sorting, square root, CORDIC sin/cos/arcsin/arccos, matrix multiplication, pseudo random number generators, fast Fourier transforms (FFTs) of lengths 32–1024, a complete k=7 Viterbi decoder, a JPEG encoder, a complete fully compliant baseband processor for an IEEE 802.11a/g wireless LAN transmitter and receiver, and a complete CAVLC compression block for an H.264 encoder.

Block diagrams of a single AsAP processor and the 6x6 AsAP 1.0 chip
Die photograph of the first generation 36-processor AsAP chip
Die photograph of the second generation 167-processor AsAP 2 chip