The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC.
In a full scan design, automatic test pattern generation (ATPG) is particularly simple.
In a chip that does not have a full scan design -- i.e., the chip has sequential circuits, such as memory elements that are not part of the scan chain, sequential pattern generation is required.
Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit.
Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational logic circuit.