The Berkeley IRAM project was a 1996–2004 research project in the Computer Science Division of the University of California, Berkeley which explored computer architecture enabled by the wide bandwidth between memory and processor made possible when both are designed on the same integrated circuit (chip).
[1] Since it was envisioned that such a chip would consist primarily of random-access memory (RAM), with a smaller part needed for the central processing unit (CPU), the research team used the term "Intelligent RAM" (or IRAM) to describe a chip with this architecture.
With strong competitive pressures, the technology employed for each component of a computer system—principally CPU, memory, and offline storage—is typically selected to minimize the cost needed to attain a given level of performance.
Microprocessor access to off-chip memory costs time and power, however, significantly limiting processor performance.
The purpose of the IRAM research project was to find if (in some computing applications) a better trade-off between cost and performance could be achieved with an architecture in which DRAM was integrated on-chip with the processor, thus eliminating the need for a redundant static memory cache—even though the technology used was not optimum for DRAM implementation.