Berkeley RISC
Berkeley's project was so successful that it became the name for all similar designs to follow; even the MIPS would become known as a "RISC processor".
[2] Both RISC and MIPS were developed from the realization that the vast majority of programs used only a small minority of a processor's available instruction set.
In a famous 1978 paper, Andrew S. Tanenbaum demonstrated that a complex 10,000 line high-level program could be represented using a simplified instruction set architecture using an 8-bit fixed-length opcode.
For instance, the National Semiconductor NS32000 started out as an effort to produce a single-chip implementation of the VAX-11, which had a rich instruction set with a wide variety of addressing modes.
To do this, RISC concentrated on adding many more registers, small bits of memory holding temporary values that can be accessed very rapidly.
The RISC designs, on the other hand, included only a single flavour of any particular instruction, the ADD, for instance, would always use registers for all operands.
This forced the programmer to write additional instructions to load the values from memory, if needed, making a RISC program "less dense".
MIPS simply added lots of registers and left it to the compilers (or assembly language programmers) to make use of them.
On the downside, this approach means that procedures with large numbers of local variables are problematic, and ones with fewer lead to registers—an expensive resource—being wasted.
The control and instruction decode section occupied only 6% of the die, whereas the typical design of the era used about 50% for the same role.
After a month of validation and debugging, the design was sent to the innovative MOSIS service for production on June 22, 1981, using a 2 μm (2,000 nm) process.
A variety of delays forced them to abandon their masks four separate times, and wafers with working examples did not arrive back at Berkeley until May 1982.
Program size was about 30% larger than the VAX but very close to that of the Z8000, validating the argument that the higher code density of CISC designs was not actually all that impressive in reality.
The programs ended up performing about the same overall number of memory accesses because the large register file dramatically improved the odds the needed operand was already on-chip.
RISC allowed for the production of a true 32-bit processor on a real chip die using what was already an older fab.
The key difference was simpler cache circuitry that eliminated one line per bit (from three to two), dramatically shrinking the register file size.
The change also required much tighter bus timing, but this was a small price to pay and in order to meet the needs several other parts of the design were sped up as well.
This simple technique yielded a surprising 30% improvement in code density, making an otherwise identical program on Blue run faster than on Gold due to the decreased number of memory accesses.
RISC II was also benched against the famous Motorola 68000, then considered to be the best commercial chip implementation, and outperformed it by 140% to 420%.
RISC is less famous, but more influential, for being the basis of the commercial SPARC processor design from Sun Microsystems.
By 1986, most large chip vendors followed, working on efforts like the Motorola 88000, Fairchild Clipper, AMD 29000 and the PowerPC.
[7] It reads Techniques developed for and alongside the idea of the reduced instruction set have also been adopted in successively more powerful implementations and extensions of the traditional "complex" x86 architecture.
