Computational RAM (C-RAM) is random-access memory with processing elements integrated on the same chip.
Some embarrassingly parallel computational problems are already limited by the von Neumann bottleneck between the CPU and the DRAM.
[3] As of 2011, the "DRAM process" (few layers; optimized for high capacitance) and the "CPU process" (optimized for high frequency; typically twice as many BEOL layers as DRAM; since each additional layer reduces yield and increases manufacturing cost, such chips are relatively expensive per square millimeter compared to DRAM) is distinct enough that there are three approaches to computational RAM: Some CPUs designed to be built on a DRAM process technology (rather than a "CPU" or "logic" process technology specifically optimized for CPUs) include The Berkeley IRAM Project, TOMI Technology[4][5] and the AT&T DSP1.
[2] A processor-in-/near-memory (PINM) refers to a computer processor (CPU) tightly coupled to memory, generally on the same silicon chip.
[6] Much of the complexity (and hence power consumption) in current processors stems from strategies to deal with avoiding memory stalls.