Adder (electronics)
An adder, or summer,[1] is a digital circuit that performs addition of numbers.
In many computers and other kinds of processors, adders are used in the arithmetic logic units (ALUs).
Other signed number representations require more logic around the basic adder.
George Stibitz invented the 2-bit binary adder (the Model K) in 1937.
The half adder adds two single binary digits
The carry signal represents an overflow into the next digit of a multi-digit addition.
The simplest half-adder design, pictured on the right, incorporates an XOR gate for
A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates.
can be derived from using a Karnaugh map to simplify the truth table.
Thus, the inputs to the final OR gate can never be both 1's (this is the only combination for which the OR and XOR outputs differ).
as its other input, and finally the carry outputs from the two half-adders are connected to an OR gate.
The sum-output from the second half adder is the final sum output (
The critical path of a full adder runs through both XOR gates and ends at the sum bit
Assumed that an XOR gate takes 1 delays to complete, the delay imposed by the critical path of a full adder is equal to: The critical path of a carry runs through one XOR gate in adder and through 2 gates (AND and OR) in carry-block and therefore, if AND or OR gates take 1 delay to complete, has a delay of: The truth table for the full adder is: Inverting all inputs of a full adder also inverts all of its outputs, which can be used in the design of fast ripple-carry adders, because there is no need to invert the carry.
[5] Various full adder digital logic circuits: It is possible to create a logical circuit using multiple full adders to add N-bit numbers.
The gate delay can easily be calculated by inspection of the full adder circuit.
[6] The general equation for the worst-case delay for a n-bit carry-ripple adder, accounting for both the sum and carry bits, is: A design with alternating carry polarities and optimized AND-OR-Invert gates can be about twice as fast.
[7][5] To reduce the computation time, Weinberger and Smith invented a faster way to add two binary numbers by using carry-lookahead adders (CLA).
[10][11] This was shown in Oklobdzija and Zeydel paper in IEEE Journal of Solid-State Circutis.
It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time.
If an adding circuit is to compute the sum of three or more numbers, it can be advantageous to not propagate the carry result.
Instead, three-input adders are used, generating two results: a sum and a carry.
After all stages of addition, however, a conventional adder (such as the ripple-carry or the lookahead) must be used to combine the final sum and carry results.
A full adder can be viewed as a 3:2 lossy compressor: it sums three one-bit inputs and returns the result as a single two-bit number; that is, it maps 8 input values to 4 output values.
(the term "compressor" instead of "counter" was introduced in[13])Thus, for example, a binary input of 101 results in an output of 1 + 0 + 1 = 10 (decimal number 2).
Likewise, a half adder can be used as a 2:2 lossy compressor, compressing four possible inputs into three possible outputs.
If the number of addends is four or more, more than one layer of compressors is necessary, and there are various possible designs for the circuit: the most common are Dadda and Wallace trees.
Since the quantum Fourier transform has a low circuit complexity, it can efficiently be used for adding numbers as well.
Within the constraints of the hardware, non-binary signals (i.e. with a base higher than 2) can be added together to calculate a sum.
Also known as a "summing amplifier",[20] this technique can be used to reduce the number of transistors in an addition circuit.
