This amplified signal is then output from the DRAM chip as well as driven back up the bit line to refresh the row.
This indeterminate signal is deflected towards high or low by the storage capacitor when a row is made active.
As an example, a typical 1 GiB SDRAM memory module might contain eight separate one-gibibit DRAM chips, each offering 128 MiB of storage space.
Each chip is divided internally into eight banks of 227=128 Mibits, each of which composes a separate DRAM array.
Accordingly, the CAS latency of an SDRAM memory module is specified in clock ticks instead of absolute time.
[citation needed] Because memory modules have multiple internal banks, and data can be output from one during access latency for another, the output pins can be kept 100% busy regardless of the CAS latency through pipelining; the maximum attainable bandwidth is determined solely by the clock speed.
For a completely unknown memory access (AKA Random access), the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it.