Due to the inherent qualities of VLSI and microelectronics, memory chips require time to fully execute commands.
These parameters (as part of a larger whole) specify the clock latency of certain specific commands issued to a random access memory.
See the SPD article for the table layout among different versions of DDR and examples of other memory timing information that is present on these chips.
Modern DIMMs include a Serial Presence Detect (SPD) ROM chip that contains recommended memory timings for automatic configuration as well as XMP/EXPO profiles of faster timing information (and higher voltages) to allow for a performance boost via overclocking.
[clarification needed] On Alder Lake CPUs and later, tRCD and tRP are no longer linked, while before Intel did not allow to set them to different values.
Higher bandwidth will also boost performance of integrated graphics processors that have no dedicated video memory but use regular RAM as VRAM.
[2][better source needed][3] A lot of it is also managed in Intel MEI, Minix OS that runs on a dedicated core in PCH.