Carbon nanotubes (CNTs) can be thought of as single atomic layer graphite sheets rolled up to form seamless cylinders.
The project named CONNECT (CarbON Nanotube compositE InterconneCTs)[6] involves the joint efforts of seven European research and industry partners on fabrication techniques and processes to enable reliable carbon nanotubes for on-chip interconnects in ULSI microchip production.
[1] Particularly their current carrying capabilities are extremely high [4] typically around 109 Acm−2 and they exhibit a ballistic length up to micrometers.
[2] However, due to the strong electron-phonon interaction in single-walled CNTs, it has been discovered that electronic current undergoes saturation at the voltage bias beyond 0.2 V.[2][3] Nevertheless, CNTs with few nm in diameter are extremely robust compared with metallic nanowires of similar diameter and demonstrate conducting properties superior as compared with copper.
Low temperature (400 °C) chemical vapor deposition growth of CNT on titanium nitride catalysed by cobalt particles has been optimized by the Fujitsu group.
For processing lines, CNT technology is more difficult because dense forests of CNTs naturally grow perpendicularly to the substrate, where they are known as vertically aligned carbon nanotube arrays.
Only few reports on horizontal lines have been published and rely on the redirection of CNT,[7][8] or the filling in existing trenches by fluidic assembly processes.
However, a recent paper [10] shows that a one-decade improvement on the conductivity may be gained just by high-pressure densification of the CNT.
In spite of the development of high-density CNT material [11] the state of the art of integrated lines is still far from the 1013 cm−2 conducting walls requested by the International Technology Roadmap for Semiconductors.
For downscaled logic and memory applications up to 14 nm node the increased current density and reliability requirements per interconnect line still have known material and integration solutions.
Thinner barrier and adhesion layers, doping of secondary metals to enhance grain boundary electromigration resistance, and integration concepts of selective cappings will be some of the adopted solutions.
However, for dimensions below 7 to 10 nm nodes, the decreased volume of available conducting metal will force innovative material and integration approaches towards novel interconnect architectures.
Also for power and high-performance applications the most critical challenges are high ampacity, thermal conductivity and electromigration resistance.
Depending on the design of the interconnect layout and the used metallization scheme, the dominance of each driving force can change.
CNTs are being studied as a potential copper replacement owing to their excellent electrical properties in terms of conductivity, ampacity and high frequency characteristics.
[15] Initial experimental realizations focused on a "bulk" approach where a mixture of CNTs and copper is deposited from a solution on the target substrate.
There are numerous methods for thermometry and the measurement of thermal conductance of devices and structures on a length scale of microns to macroscopic.
Scanning thermal microscopy and thermometry [30] is the most promising technique for its versatility, but restrictions in tip fabrication, operation modes and signal sensitivity have limited the resolutions to 10 nm in the most cases.
To increase the resolution of such technique is an open challenge which is attracting lot of attention from the industry and scientific community.
[32][33][6] From a macroscopic point of view, a generalized compact RLC model for CNT interconnects can be depicted as in,[34] where the model of an individual multi-wall carbon nanotube is shown with parasitics representing both dc conductance and high-frequency impedance i.e. inductance and capacitance effects.
Detailed simulation for signal interconnects have been performed by Naeemi et al.,[35][36][37] and it has been shown that CNTs have lower parasitics than copper metal lines, however, the contact resistance between CNT-to-CNT and CNT-to-metal is large and can be detrimental for timing issues.
[39] The macroscopic circuit simulation addresses just the interconnect performance neglecting other important aspects like reliability and variability of CNTs, which can be properly treated only at mesoscopic level by means of fully three dimensional Technology Computer Aided Design modelling approaches.
Further potential modeling improvements include the self-consistent simulation of the interaction between electronic and thermal transport in CNTs, but also in copper-CNT composite lines and CNT contacts with metals and other relevant materials.
The CNTs with encapsulated nanowires have been studied at the ab initio level with self-consistent treatment of electronic and phonon transport and demonstrated to improve current-voltage performance.