Instruction set architecture
For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but they have radically different internal designs.
Prior to NPL [System/360], the company's computer designers had been free to honor cost objectives not only by selecting technologies but also by fashioning functional and architectural refinements.
The SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors spanning a wide range of cost and performance.
None of the five engineering design teams could count on being able to bring about adjustments in architectural specifications as a way of easing difficulties in achieving cost and performance objectives.
In addition, these virtual machines execute less frequently used code paths by interpretation (see: Just-in-time compilation).
A reduced instruction set computer (RISC) simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.
These architectures seek to exploit instruction-level parallelism with less hardware than RISC and CISC by making the compiler responsible for instruction issue and scheduling.
SIMD instructions allow easy parallelization of algorithms commonly involved in sound, image, and video processing.
Some exotic instruction sets do not have an opcode field, such as transport triggered architectures (TTA), only operand(s).
The instruction set carries out most ALU actions with postfix (reverse Polish notation) operations that work only on the expression stack, not on data registers or arbitrary main memory cells.
This can be very convenient for compiling high-level languages, because most arithmetic expressions can be easily translated into postfix notation.
Computers with high code density often have complex instructions for procedure entry, parameterized returns, loops, etc.
However, more typical, or frequent, "CISC" instructions merely combine a basic ALU operation, such as "add", with the access of one or more operands in memory (using addressing modes such as direct, indirect, indexed, etc.).
Certain architectures may allow two or three operands (including the result) directly in memory or may be able to perform functions such as automatic pointer increment, etc.
Reduced instruction-set computers, RISC, were first widely implemented during a period of rapidly growing memory subsystems.
They sacrifice code density to simplify implementation circuitry, and try to increase performance via higher clock frequencies and more registers.
However, as RISC computers normally require more and often longer instructions to implement a given task, they inherently make less optimal use of bus bandwidth and cache memories.
Certain embedded RISC ISAs like Thumb and AVR32 typically exhibit very high density owing to a technique called code compression.
However, a more complex set may optimize common operations, improve memory and cache efficiency, or simplify programming.
Some instruction set designers reserve one or more opcodes for some kind of system call or software interrupt.
[dubious – discuss] On systems with multiple processors, non-blocking synchronization algorithms are much easier to implement[citation needed] if the instruction set includes support for something such as "fetch-and-add", "load-link/store-conditional" (LL/SC), or "atomic compare-and-swap".
The various ways of implementing an instruction set give different tradeoffs between cost, performance, power consumption, size, etc.
Some kind of register transfer language is then often used to describe the decoding and sequencing of each instruction of an ISA using this physical microarchitecture.
There are two basic ways to build a control unit to implement this description (although many designs use middle ways or compromises): Some microcoded CPU designs with a writable control store use it to allow the instruction set to be changed (for example, the Rekursiv processor and the Imsys Cjip).
The demands of high-speed digital signal processing have pushed in the opposite direction—forcing instructions to be implemented in a particular way.
