Control unit

[1] In modern computer designs, the control unit is typically an internal part of the CPU with its overall role and operation unchanged since its introduction.

Multicycle control units typically use both the rising and falling edges of their square-wave timing clock.

An interrupt occurs because some type of input or output needs software attention in order to operate correctly.

If a quick response is most important, a control unit is designed to abandon work to handle the interrupt.

In a pipelined computer, the control unit arranges for the flow to start, continue, and stop as a program commands.

When a program makes a decision, and switches to a different sequence of instructions, the pipeline sometimes must discard the data in process and restart.

For example, even simple control units can assume that a backwards branch, to a lower-numbered, earlier instruction, is a loop, and will be repeated.

Designers vary the number of threads depending on current memory technologies and the type of computer.

Typical computers such as PCs and smart phones usually have control units with a few threads, just enough to keep busy with affordable memory systems.

In general-purpose CPUs like PCs and smartphones, the threads are usually made to look very like normal time-sliced processes.

In GPUs, the thread scheduling usually cannot be hidden from the application software, and is often controlled with a specialized subroutine library.

When the execution of calculations is the slowest, instructions flow from memory into pieces of electronics called "issue units."

An alternative style of issuing control unit implements the Tomasulo algorithm, which reorders a hardware queue of instructions.

[6][7] With some additional logic, a scoreboard can compactly combine execution reordering, register renaming and precise exceptions and interrupts.

The advantage is that an out of order computer can be simpler in the bulk of its logic, while handling complex multi-step instructions.

x86 Intel CPUs since the Pentium Pro translate complex CISC x86 instructions to more RISC-like internal micro-operations.

The "back" of the CU is an out-of-order CPU that issues the micro-operations and operands to the execution units and data paths.

Many modern low-power CMOS CPUs stop and start specialized execution units and bus interfaces depending on the needed instruction.

Some computers[9] even arrange the CPU's microarchitecture to use transfer-triggered multiplexers so that each instruction only utilises the exact pieces of logic needed.

A similar method is used in most PCs, which usually have an auxiliary embedded CPU that manages the power system.

Some vendors use this technique in selected portions of an IC by constructing low leakage logic from large transistors that some processes provide for analog circuits.

Special transistor doping materials (e.g. hafnium) can also reduce leakage, but this adds steps to the processing, making it more expensive.

Managing leakage is more difficult, because before the logic can be turned-off, the data in it must be moved to some type of low-leakage storage.

When the CPU enters a power saving mode (e.g. because of a halt that waits for an interrupt), data is transferred to the low-leakage cells, and the others are turned off.

When the memory, bus or cache is shared with other CPUs, the control logic must communicate with them to assure that no computer ever gets out-of-date old data.

In later production computers, the most common use of a front panel was to enter a small bootstrap program to read the operating system from disk.

Most PDP-8 models had a data bus designed to let I/O devices borrow the control unit's memory read and write logic.

Previously, control units for CPUs used ad hoc logic, and they were difficult to design.

[15] The idea of microprogramming was introduced by Maurice Wilkes in 1951 as an intermediate level to execute computer program instructions.

This is a logical truth table, that translates a microcode address into the control unit outputs.

Animation of the control matrix of a simple hardwired control unit performing an LDA-instruction