Depletion and enhancement modes

For N-type depletion-load devices, the threshold voltage might be about −3 V, so it could be turned off by pulling the gate 3 V negative (the drain, by comparison, is more positive than the source in NMOS).

[1] Moving the gate voltage toward the drain voltage "enhances" the conduction in the channel, so this defines the enhancement mode of operation, while moving the gate away from the drain depletes the channel, so this defines depletion mode.

Logic families built in older processes that did not support depletion-mode transistors were retrospectively referred to as enhancement-load logic, or as saturated-load logic, since the enhancement-mode transistors were typically connected with gate to the VDD supply and operated in the saturation region (sometimes the gates are biased to a higher VGG voltage and operated in the linear region, for a better power–delay product (PDP), but the loads then take more area).

The original two types of MOSFET logic gates, PMOS and NMOS, were developed by Frosch and Derick in 1957 at Bell Labs.

[4] In 1966, T. P. Brody and H. E. Kunig at Westinghouse Electric fabricated enhancement- and depletion-mode indium arsenide (InAs) MOS thin-film transistors (TFTs).