The added features make it easier to develop and apply manufacturing tests to the designed hardware.
Automatic test pattern generation (ATPG) is much easier if appropriate DFT rules and suggestions have been implemented.
Over the years the industry has developed and used a large variety of more or less detailed and more or less formal guidelines for desired and/or mandatory DFT circuit modifications.
Most tool-supported DFT practiced in the industry today, at least for digital circuits, is predicated on a Structural test paradigm.
While the task of testing a single logic gate at a time sounds simple, there is an obstacle to overcome.
To simplify test generation, DFT addresses the accessibility problem by removing the need for complicated state transition sequences when trying to control and/or observe what's happening at some internal circuit element.
One challenge for the industry is keeping up with the rapid advances in chip technology (I/O count/size/placement/spacing, I/O speed, internal circuit count/speed/power, thermal control, etc.)
As a result, DFT techniques are continually being updated, such as incorporation of compression, in order to make sure that tester application times stay within certain bounds dictated by the cost target for the products under test.
Especially for advanced semiconductor technologies, it is expected some of the chips on each manufactured wafer contain defects that render them non-functional.
In both cases, vital information about the nature of the underlying problem may be hidden in the way the chips fail during test.
In scan-design, registers (flip-flops or latches) in the design are connected in one or more scan chains, which are used to gain access to internal nodes of the chip.
Straightforward application of scan techniques can result in large vector sets with corresponding long tester time and memory requirements.
Large gains are possible since any particular test vector usually only needs to set and/or examine a small fraction of the scan chain bits.
The output of a scan design may be provided in forms such as Serial Vector Format (SVF), to be executed by test equipment.
At this point the full internal state can be dumped out, or set to any desired values, by use of the scan chains.