It was packaged in a 28-pin DIP which made it less expensive to implement than contemporary designs like the 40-pin MOS 6502 and Zilog Z80.

This was not a significant limitation at the time, as memory was still very expensive and the target market could often make do with the internal RAM.

Electronic Arrays (EA) had problems with the new depletion-load NMOS logic fabrication line and struggled with deliveries.

[2] However, other companies had continually beat them to market with reduced chip counts, first Mostek and Texas Instruments, and later a number of Japanese electronics firms.

As most systems would have little or no external RAM and small programs in ROM, it was also common to use smaller address spaces as this allowed the number of pins to be reduced, which simplified circuit board layout.

[5] Another major change taking place in the mid-1970s was the introduction of depletion-load NMOS logic design.

Previous fabrication systems using "enhancement-load" circuits required three input voltages, one of which was typically +12V.

[8] This allowed a simple controller to be implemented in two chips, the 9002 and a ROM, along with any required interface hardware like an Intel 8212 or even just a flip-flop.

[9][3] Unfortunately for Electronic Arrays, ramping up the depletion-load fabrication line did not go as well as it did for companies like MOS Technology, and by the end of 1976 they were still struggling with yields.

[14] One electronics company, the Pro-Log Corporation of Monterey, California, used the 9002 in a single-board computer in early 1977.

However, by the time the second edition was published in 1977, the chapters covering the EA9002 and Rockwell PPS-8 were removed as the former had been cancelled and the latter never released.

[17] Separate instructions were also needed to read and write the internal scratch RAM, which otherwise operated like external memory and had to be loaded and saved through the accumulator using RDS and WRS.