It had a number of unique design features, which Adam Osborne described as "most unusual... more powerful... also one of the most difficult to understand.
"[1] It was released with a suite of support chips, including ROM and RAM, parallel and serial controllers, and a direct memory access (DMA) system.
The simpler Rockwell PPS-4 did not suffer the same fate, finding a number of roles in low-end systems and being produced into the 1980s.
This was used as a form of short addressing, which was more commonly seen in other processors as a "zero page" or "base page", the idea being that only a single byte was needed to specify and address and thus save memory in the program code and the time needed to load an extra byte in the instruction.
While small by standards set by processors like the Zilog Z80 or even the MOS 6502, this size of stack is suitable for systems that generally used it only for subroutine calls into ROM or interrupt handlers.
Most processors of the era had additional status bits to indicate the outcome of comparisons, like whether the value in A is zero, but in the PPS-8 these were combined with the branch instructions so they did not have to be user-visible.
As was typical for the era, the PPS-8 included instructions for directly working with binary coded decimal (BCD) data.
Not only did the PPS-8 offer BCD addition and subtraction, it also had instructions that shifted (rolled) an 8-bit value by 4-bits, making it easier to extract individual digits.
The load/store operations generally came in five versions, the base instructions, L(oad), S(tore) or X(change), which used the addresses referred to data memory pointed to in Z+X.
Finally, the NCX instruction incremented X and then compared it with Y as the decision of whether or not the branch was complete, rather than crossing zero, and DCX was the same with a decrement.
[15] Finally, the first half of page one held the "subroutine entry pool", a list of addresses in program memory.
The entire multi-chip system, including RAM and ROM, used only two control pins along with the clock signals.
The system supported vectored interrupts; when one of these pins is pulled high, the processor finishes the current instruction, swaps the PC onto L, and then calls the code located at an address stored in the first three slots in the subroutine entry pool.
PO (power on) was the reset pin, which cleared the contents of all of the registers and began executing the instruction at address zero.
Among these was a 2 kB ROM, a 256 byte RAM, the GPIO, PDC, DMAC, SDC and some device controllers.
[19] The GPIO also passes through one clock signal on the A pin to allow external devices to match the timing of the system.
[22] The DMAC, for DMA controller, was the only I/O chip that had connections to the address bus, allowing it to access data memory as an equal partner with the CPU.
When the CPU completed its current operation it would pull the DMRA low again, and the DMAC was then free to take over the bus.
It then uses the DMA0 pin to signal the PDC to activate that device, reads or writes a value from channel B, and places the result on the data bus.
It is the combination of signals from the DMAC to present an address and PDC to read or write on the data bus that completes the transfer.
DMAC could operate in two basic modes, a one-off mode in which the chip reads data from a device when it receives a signal on one of the device DMA line and then uses cycle stealing to transmit it to memory and decrements the counter, or in a permanent mode that mapped an area of memory to a particular device, which operates in a similar fashion but then resets the buffer length and address to the original values when the transfer is complete.
In general terms this is a three-output, two-input UART that includes additional logic to allow it to trigger the DMAC to perform the transfer into memory.
For instance, one could set up the DMAC with a base address and buffer length, set up the SDC to read from device 1 with a particular setup like 8 bit data with 1 start and stop bit, and then whenever the SDC has received a full byte it will signal the DMAC to transfer it.
[11] A PPS-8 assembler and emulator was hosted on Tymshare, GEnie and Rockwell's Time Sharing Option system.
The basic concept was not unusual at the time, processors such as the Signetics 2650 and EA9002 had similar features in which an address had to be expressed as multiple parts that produced a series of blocks or pages.
The Rockwell documentation shows a basic system layout containing the clock chip, CPU, DMAC, PDC, SDC, several device controllers, and a user-selected amount of RAM and ROM.
[27] In contrast, something like the two-chip Fairchild F8 included ROM and RAM, and three parallel ports that could also be used as serial lines or controllers like GPIO.