z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit complex instruction set computer (CISC) instruction set architecture, implemented by its mainframe computers.
[2] However, all 24-bit and 31-bit problem-state application programs originally written to run on the ESA/390 architecture will be unaffected by this change.
The z13 implementation includes two independent SIMD units to operate on vector data.
The new instruction provide tensor operations useful for AI and neural network applications.
For details on which fields are dependent on specific features, consult the Principles of Operation.
only) The FPC register contains Interrupt Masks (IM), Status Flags (SF), Data Exception Code (DXC), Decimal Rounding Mode (DRM) and Binary Rounding Mode (BRM).
The PSW holds the instruction address and other fields reflecting the status of the program currently running on a CPU.
IBM's operating systems z/OS, z/VSE, z/TPF, and z/VM are versions of MVS, VSE, Transaction Processing Facility (TPF), and VM that support z/Architecture.
This allows software developers to choose the address size that is most advantageous for their applications and data structures.
Earlier announcements of System z10 simply specified that it implements z/Architecture with some additions: 50+ new machine instructions, 1 MB page frames, and hardware decimal floating point unit (HDFU).
Unlike an address space, a dataspace or hiperspace contains only user data; it does not contain system control blocks or common areas.
IBM Mainframe processors through much of the 1980s and 1990s supported another kind of memory: Expanded Storage.
The overhead of moving single and groups of pages between Central and Expanded Storage was reduced with the introduction of the MVPG (Move Page) instruction and the ADMF (Asynchronous Data Mover Facility) capability.
Some uses are namely: Until the mid-1990s Central and Expanded Storage were physically different areas of memory on the processor.
Since the mid-1990s Central and Expanded Storage were merely assignment choices for the underlying processor memory.
These choices were made based on specific expected uses: For example, Expanded Storage is required for the Hiperbatch function (which uses the MVPG instruction to access its hiperspaces).
[31]: Note 8, page 7–27 [32] The need to move more than 256 bytes within main memory had historically been addressed with software[33] (MVC loops), MVCL,[34] which was introduced with the 1970 announcement of the System/370, and MVPG, patented[35] and announced by IBM in 1989, each have advantages.
A macro instruction named IOSADMF, which has been described as an API that avoids "direct, low-level use of ADMF",[38] can be used to read[h] or write data to or from a hiperspace.
"[40] Platform Solutions Inc. (PSI) previously marketed Itanium-based servers which were compatible with z/Architecture.