Maximum limits on fan-out are usually stated for a given logic family or device in the manufacturer's datasheets.
More complex analysis than fan-in and fan-out is required when two different logic families are interconnected.
Ultimately, whether a device has the fan-out capability to drive (with guaranteed reliability) a set of inputs is determined by adding up all the input-low (max.)
source currents specified on the datasheets of the driven devices, adding up all the input-high (max.)
However, for any reputable manufacturer, if this current analysis reveals that the device cannot drive the inputs, the fan-out number will agree.
However, since real-world fabrication technologies exhibit less than perfect characteristics, a limit will be reached where a gate output cannot drive any more current into subsequent gate inputs - attempting to do so causes the voltage to fall below the level defined for the logic level on that wire, causing errors.
However, inputs of real gates have capacitance as well as resistance to the power supply rails.
This capacitance will slow the output transition of the previous gate and hence increase its propagation delay.
People who design digital integrated circuits typically insert trees whenever necessary such that the fan-in and fan-out of each and every gate on the chip is between 2 and 10.
If this trace length condition can't be met, then the microcontroller must be run at a slower bus speed for reliable operation, or a buffer chip with higher current drive must be inserted into the circuit.