Core voltage was decreased to 1.5 V. Data Bus Inversion adds an additional active-low DBI# pin to the address/command bus and each byte of data.
On the signaling front, GDDR4 expands the chip I/O buffer to 8 bits per two cycles, allowing for greater sustained bandwidth during burst transmission, but at the expense of significantly increased CAS latency (CL), determined mainly by the double reduced count of the address/command pins and half-clocked DRAM cells, compared to GDDR3.
The number of addressing pins was reduced to half that of the GDDR3 core, and were used for power and ground, which also increases latency.
In Samsung's GDDR4 SDRAM datasheet, it was referred as 'GDDR4 SGRAM', or 'Graphics Double Data Rate version 4 Synchronous Graphics RAM'.
However, the essential block write feature is not available, so it is not classified as SGRAM.