IP cores are commonly offered as synthesizable RTL in a hardware description language such as Verilog or VHDL.
The netlist is a Boolean-algebra representation of the IP's logical function implemented as generic gates or process-specific standard cells.
[citation needed] Analog and mixed-signal logic are generally distributed as hard cores.
offer various hard-macro IP functions built for their own foundry processes, helping to ensure customer lock-in.
Further, x86 leaders Intel and AMD heavily protect their processor designs' intellectual property and don't use this business model for their x86-64 lines of microprocessors.
IP cores are also licensed for various peripheral controllers such as for PCI Express, SDRAM, Ethernet, LCD display, AC'97 audio, and USB.
"Hardwired" (as opposed to software programmable soft microprocessors described above) digital logic IP cores are also licensed for fixed functions such as MP3 audio decode, 3D GPU, digital video encode/decode, and other DSP functions such as FFT, DCT, or Viterbi coding.
Gartner Group estimated the total value of sales related to silicon intellectual property at US $1.5 billion in 2005 with annual growth expected around 30%.
[3][needs update] IP hardening is a process to re-use proven designs and generate fast time-to-market, low-risk-in-fabrication solutions to provide intellectual property (IP) (or silicon intellectual property) of design cores.
For example, a digital signal processor (DSP) is developed from soft cores of RTL format, and it can be targeted to various technologies or different foundries to yield different implementations.
The effort to harden soft IP requires employing the quality of the target technology, goals of design and the methodology.
E.g. the hard core in GDS II format is said to clean in DRC (design rule checking), and LVS (see Layout versus schematic).