The GDDR5 interface transfers two 32-bit wide data words per write clock (WCK) cycle to/from the I/O pins.

Corresponding to the 8N-prefetch, a single write or read access consists of a 256-bit wide two CK clock cycle data transfer at the internal memory core and eight corresponding 32-bit wide one-half WCK clock cycle data transfers at the I/O pins.

A differential command clock (CK) as a reference for address and command inputs, and a forwarded differential write clock (WCK) as a reference for data reads and writes, that runs at twice the CK frequency.

A single 32-bit GDDR5 chip has about 67 signal pins and the rest are power and grounds in the 170 BGA package.

[2] Hynix Semiconductor introduced the industry's first 60 nm class "1 Gb" (10243 bit) GDDR5 memory in 2007.

In November 2007, Qimonda, a spin-off of Infineon, demonstrated and sampled GDDR5,[4] and released a paper about the technologies behind GDDR5.

The new chip can work at up to 7 GHz effective clock-speed and will be used in graphics cards and other high bandwidth memory applications.

On February 20, 2013, it was announced that the PlayStation 4 would use sixteen 4 Gb GDDR5 memory chips for a total of 8 GB of GDDR5 @ 176 Gbit/s (CK 1.375 GHz and WCK 2.75 GHz) as combined system and graphics RAM for use with its AMD-powered system on a chip comprising 8 Jaguar cores, 1152 GCN shader processors and AMD TrueAudio.

[19] As of January 15, 2015, Samsung announced in a press release that it had begun mass production of "8 Gb" (8 × 10243 bits) GDDR5 memory chips based on a 20 nm fabrication process.

[20] On January 6, 2015, Micron Technology President Mark Adams announced the successful sampling of 8 Gb GDDR5 on the company's fiscal Q1-2015 earnings call.

[23][24][25] The formal announcement of Micron's 8 Gb GDDR5 appeared in the form of a blog post Archived 2015-09-07 at the Wayback Machine by Kristopher Kido on the company's website September 1, 2015.