Harvard architecture

[2][3] The term is often stated as having originated from the Harvard Mark I[4] relay-based computer, which stored instructions on punched tape (24 bits wide) and data in electro-mechanical counters.

However, in the only peer-reviewed paper on the topic published in 2022 the author states that:[5][6] Modern processors appear to the user to be systems with von Neumann architectures, with the program code stored in the same main memory as the data.

Harvard architecture is historically, and traditionally, split into two address spaces, but having three, i.e. two extra (and all accessed in each cycle) is also done,[7] while rare.

In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time,[8] even without a cache.

A Harvard architecture computer can thus be faster for a given circuit complexity because instruction fetches and data access do not contend for a single memory pathway.

When accessing backing memory, it acts like a von Neumann machine (where code can be moved around like data, which is a powerful technique).

The solution is to provide a small amount of very fast memory known as a CPU cache which holds recently accessed data.

[b] Modern high performance CPU chip designs incorporate aspects of both Harvard and von Neumann architecture.

Relatively pure Harvard architecture machines are used mostly in applications where trade-offs, like the cost and power savings from omitting caches, outweigh the programming penalties from featuring distinct code and data address spaces.