In digital logic, a hazard is an undesirable effect caused by either a deficiency in the system or external influences in both synchronous[citation needed] and asynchronous circuits.
Hazards are a temporary problem, as the logic circuit will eventually settle to the desired function.
Therefore, in synchronous designs, it is standard practice to register the output of a circuit before it is being used in a different clock domain or routed out of the system, so that hazards do not cause any problems.
Now we know roughly how the hazard is occurring, for a clearer picture and the solution on how to solve this problem, we would look to the Karnaugh map.
A theorem proved by Huffman[2] tells us that adding a redundant loop 'BC' will eliminate the hazard.
The amended function is: Now we can see that even with imperfect logic elements, our example will not show signs of hazards when A changes state.
Dynamic hazards often occur in larger logic circuits where there are different routes to the output (from the input).