Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs.
In computer programming, addressing modes are primarily of interest to those who write in assembly languages and to compiler writers.
For example, some complex instruction set computer (CISC) architectures, such as the Digital Equipment Corporation (DEC) VAX, treat registers and literal or immediate constants as just another addressing mode.
The instructions shown below are purely representative in order to illustrate the addressing modes, and do not necessarily reflect the mnemonics used by any particular computer.
Computer architectures vary greatly as to the number of addressing modes they provide in hardware.
[10][11] This calculates the effective operand address and loads it into a register, without accessing the memory it refers to.
Measurements of actual programs suggest that an 8 or 10 bit offset is large enough for some 90% of conditional jumps (roughly ±128 or ±512 bytes).
Many features in modern CPUs—instruction prefetch and more complex pipelineing, out-of-order execution, etc.—maintain the illusion that each instruction finishes before the next one begins, giving the same final results, even though that's not exactly what happens internally.
Such CPUs have an instruction pointer that holds that specified address; it is not a program counter because there is no provision for incrementing it.
Such CPUs include some drum memory computers such as the IBM 650, the SECD machine, Librascope RPC 4000, and the RTX 32P.
[14] On processors implemented with horizontal microcode, the microinstruction may contain the high order bits of the next instruction address.
Other computing architectures go much further, attempting to bypass the von Neumann bottleneck using a variety of alternatives to the program counter.
However, the principle of locality of reference applies: over a short time span, most of the data items a program wants to access are fairly close to each other.
Example 1: Within a subroutine a programmer will mainly be interested in the parameters and the local variables, for which one base register (the frame pointer) usually suffices.
Andrew Tanenbaum showed that 98% of all the constants in a program would fit in 13 bits (see RISC design philosophy).
Among the x86 instructions, some use implicit registers for one of the operands or results (multiplication, division, counting conditional jump).
Some RISC machines have a special Load Upper Literal instruction which places a 16- or 20-bit constant in the top half of a register.
The start of the array is stored in the literal address (perhaps modified at program-load time by a relocating loader) of the instruction that references it.
This addressing mode dynamically scales the value in the index register to allow for the size of each array element, e.g. if the array elements are double precision floating-point numbers occupying 8 bytes each then the value in the index register is multiplied by 8 before being used in the effective address calculation.
For example, (A7) After determining the effective address, the value in the base register is incremented by the size of the data item that is to be accessed.
Indirect addressing does carry a performance penalty due to the extra memory access involved.
Some early minicomputers (e.g. DEC PDP-8, Data General Nova) had only a few registers and only a limited direct addressing range (8 bits).
The PC-relative addressing mode can be used to load a register with a value stored in program memory a short distance away from the current instruction.
The IBM z/Architecture includes specific instructions, e.g., Load Relative Long, with PC-relative addressing if the General-Instructions-Extension Facility is active.
The IBM 1620, the Data General Nova, the HP 2100 series, and the NAR 2 each have such a multi-level memory indirect, and could enter such an infinite address calculation loop.
[26] So, an indirect address loop would not prevent execution of device service routines, including any preemptive multitasking scheduler's time-slice expiration handler.
Later models of the DEC PDP-11 series mapped the registers onto addresses in the input/output area, but this was primarily intended to allow remote diagnostics.
[29] This made it easy to step through memory in a loop without needing to use the accumulator to increment the address.
Given that opcodes on these processors were only one byte (8 bits) in length, memory addresses could make up a significant part of code size.
The zero page address mode was enhanced in several late model 8-bit processors, including the WDC 65816, the CSG 65CE02, and the Motorola 6809.