The InfiniteReality was marketed to and used by large organizations such as companies and universities that are involved in computer simulation, digital content creation, engineering and research.

It was designed to render complex scenes in high-quality at 60 frames per second, roughly two to four times the performance of the RealityEngine it replaced.

[1] The implementation comprises twelve ASIC designs fabricated in 0.5 and 0.35 micrometre processes with three layers of metal interconnect.

In multi-seat mode, each pipeline can serve up to eight simultaneous users, each with their own separate displays, keyboards and mice.

The second method uses MonsterMode software to distribute the data used to render a frame to multiple pipelines.

Due to the InfiniteReality being designed for two very different platforms, the traditional shared memory bus-based Onyx using the POWERpath-2 bus, and the distributed shared memory network-based Onyx2 using the NUMAlink2 interconnect, the InfiniteReality had to have an interface that could provide similar performance on both platforms, which had a large difference in incoming bandwidth (200 MB/s versus 400 MB/s respectively).

[1] To this end, a Host Interface Processor, an embedded RISC core, is used to fetch display list objects using direct memory access (DMA).

The Geometry Engine is a semi-custom ASIC with a single instruction multiple data (SIMD) pipeline containing three floating-point cores, each containing an arithmetic logic unit (ALU), a multiplier and a 32-bit by 32-entry register file with two read and two write ports.

The Geometry Engine uses a 195-bit microinstruction, which is compressed in order to reduce size and bandwidth usage in return for slightly less performance.

The Geometry Engine processor operates at 90 MHz, achieving a maximum theoretical performance of 540 MFLOPS.

The FIFO is built from SDRAM and has a capacity of 4 MB,[3] large enough to store 65,536 vertexes.

Each TM ASIC controls four SDRAMs that make up one-eighth of the texture memory.

To achieve this, the TM and TF ASICs implement a two-rank omega network, which reduces the number of individual paths required for the 32 to 80 sort while maintaining the same functionality.

Firstly, each Image Engine controls a portion of the raster memory, which in the case of the InfiniteReality, is a 1 MB SGRAM organized as 262,144 by 32-bit words.

If one Raster Manager board is present in the pipeline, the Image Engine uses the entire width of the bus, whereas if two or more Raster Manager boards are present, the Image Engine uses half the bus.

Four Image Engine "cores" are contained on an Image Engine ASIC, which contains nearly 488,000 logic gates, comprising 1.95 million transistors, on a 42 mm2 (6.5 by 6.5 mm) die that was fabricated in a 0.35 micrometre process by VLSI Technology.

Each pipeline is capable of display resolutions of 2.62, 5.24 or 10.48 million pixels, provided that one, two or four Raster Manager boards respectively are present.

Instead of being connected to the host system via a FCI cable, the board set is plugged into the rear of a midplane, which can support two pipelines.

The new Raster Manager board operated at 72 MHz,[6] improving anti-aliased pixel fill performance.

It is the last member of the InfiniteReality family, itself succeeded by the ATI FireGL-based UltimateVision, which was used in the Onyx4.

[7] The figures presented in the tables are for a minimal 1-pipeline and a maximal 16-pipeline configuration, except for the Reality, which was restricted to single pipe operation.