System on a chip
[1] SoCs may contain digital and also analog, mixed-signal and often radio frequency signal processing functions (otherwise it may be considered on a discrete application processor).
[2] An SoC usually integrates a microcontroller, microprocessor or perhaps several processor cores with peripherals like a GPU and a Wi-Fi receiver and more coprocessors.
Compared to a multi-chip architecture, an SoC with equivalent functionality will have reduced power consumption as well as a smaller semiconductor die area.
However, they are typically used in mobile computing such as tablets, smartphones, smartwatches, and netbooks as well as embedded systems and in applications where previously microcontrollers would be used.
[5] Applications include AI acceleration, embedded machine vision,[6] data collection, telemetry, vector processing and ambient intelligence.
Often embedded SoCs target the internet of things, multimedia, networking, telecommunications and edge computing markets.
The ARM7500 chip was their second-generation SoC, based on the ARM700, VIDC20 and IOMD controllers, and was widely licensed in embedded devices such as set-top-boxes, as well as later Acorn personal computers.
[13] Historically, a shared global computer bus typically connected the different components, also called "blocks" of the SoC.
Wire delay is not scalable due to continued miniaturization, system performance does not scale with the number of cores attached, the SoC's operating frequency must decrease with each additional core attached for power to be sustainable, and long wires consume large amounts of electrical power.
[13]: xiii In the late 2010s, a trend of SoCs implementing communications subsystems in terms of a network-like topology instead of bus-based protocols has emerged.
A trend towards more processor cores on SoCs has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost.
[13]: xiii Networks-on-chip have advantages including destination- and application-specific routing, greater power efficiency and reduced possibility of bus contention.
[13] A system on a chip consists of both the hardware, described in § Structure, and the software controlling the microcontroller, microprocessor or digital signal processor cores, peripherals and interfaces.
[15] Other components can remain software and be compiled and embedded onto soft-core processors included in the SoC as modules in HDL as IP cores.
This process is called functional verification and it accounts for a significant portion of the time and energy expended in the chip design life cycle, often quoted as 70%.
[18][19] With high capacity and fast compilation time, simulation acceleration and emulation are powerful technologies that provide wide visibility into systems.
[citation needed] FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system's full operating frequency with real-world stimuli.
In parallel, the hardware elements are grouped and passed through a process of logic synthesis, during which performance constraints, such as operational frequency and expected signal delays, are applied.
These netlists are combined with the glue logic connecting the components to produce the schematic description of the SoC as a circuit which can be printed onto a chip.
This process is known as place and route and precedes tape-out in the event that the SoCs are produced as application-specific integrated circuits (ASIC).
If optimization was not necessary, the engineers would use a multi-chip module architecture without accounting for the area use, power consumption or performance of the system to the same extent.
Customers want long battery lives for mobile computing devices, another reason that power consumption must be minimized in SoCs.
[21]: 2–9 In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system.
Due to increased transistor densities as length scales get smaller, each process generation produces more heat output than the last.
Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneous heat fluxes, which cannot be effectively mitigated by uniform passive cooling.
This can be accomplished by laying out elements with proper proximity and locality to each-other to minimize the interconnection delays and maximize the speed at which data is communicated between modules, functional units and memories.
Task scheduling is an important activity in any computer system with multiple processes or threads sharing a single processor core.
It is important to reduce § Latency and increase § Throughput for embedded software running on an SoC's § Processor cores.
Markov chain modeling allows asymptotic analysis of the SoC's steady state distribution of power, heat, latency and other factors to allow design decisions to be optimized for the common case.
SoCs can be fabricated by several technologies, including: ASICs consume less power and are faster than FPGAs but cannot be reprogrammed and are expensive to manufacture.
