Hardware emulation

The largest portion of silicon integrated circuit respins and steppings are due at least in part to functional errors and bugs inadvertently introduced at the RTL stage of the design process.

Functional verification of a design is most often performed using logic simulation and/or prototyping on field-programmable gate arrays (FPGAs).

FPGA-based prototypes are fast and inexpensive, but the time required to implement a large design into several FPGAs can be very long and is error-prone.

A high-bandwidth, low latency channel connects the workstation to the accelerator to exchange signal data between testbench and design.

In-circuit emulation improves somewhat on FPGA prototyping's implementation times, and provides a comprehensive, efficient debugging capability.

At 10,000 to 100,000 times the speed of simulation, emulation makes it possible to test application software while still providing a comprehensive hardware debug environment.

High end hardware emulators provide a debugging environment with many features that can be found in logic simulators, and in some cases even surpass their debugging capabilities: Another difference between simulation and acceleration and emulation is a consequence of accelerators using hardware for implementation – they have only two logic states – acting the way the silicon will when fabricated.

New tools that enable full RTL signal visibility with a small FPGA LUT impact, allow deep capture depth and provide multi-chip and clock domain analysis are emerging to allow efficient debug, comparable to the emulator.