A word is a fixed-sized datum handled as a unit by the instruction set or the hardware of the processor.
The size of a word is reflected in many aspects of a computer's structure and operation; the majority of the registers in a processor are usually word-sized and the largest datum that can be transferred to and from the working memory in a single operation is a word in many (not all) architectures.
[1] The size of a word can sometimes differ from the expected due to backward compatibility with earlier computers.
If multiple compatible variations or a family of processors share a common architecture and instruction set but differ in their word sizes, their documentation and software may become notationally complex to accommodate the difference (see Size families below).
A common choice then was the 36-bit word, which is also a good size for the numeric properties of a floating point format.
Depending on the machine and the instruction, the length might be denoted by a count field, by a delimiting character, or by an additional bit called, e.g., flag, or word mark.
Instruction execution takes a variable number of cycles, depending on the size of the operands.
When the workload involves processing fields of different sizes, it can be advantageous to address to the bit.
Instructions could automatically adjust the pointer to the next byte on, for example, load and deposit (store) operations.
The commonly used sizes are usually a power of two multiple of the unit of address resolution (byte or word).
As computer designs have grown more complex, the central importance of a single word size to an architecture has decreased.
Also, similar to how bytes are used for small numbers in many programs, a shorter word (16 or 32 bits) may be used in contexts where the range of a wider word is not needed (especially where this can save considerable stack space or cache memory space).
Data structures containing such different sized words refer to them as: A similar phenomenon has developed in Intel's x86 assembly language – because of the support for various sizes (and backward compatibility) in the instruction set, some instruction mnemonics carry "d" or "q" identifiers denoting "double-", "quad-" or "double-quad-", which are in terms of the architecture's original 16-bit word size.
The z/Architecture, which is the 64-bit member of that architecture family, continues to refer to 16-bit halfwords, 32-bit words, and 64-bit doublewords, and additionally features 128-bit quadwords.
Often carefully written source code – written with source-code compatibility and software portability in mind – can be recompiled to run on a variety of processors, even ones with different data word lengths or different address widths or both.