This is in contrast to a von Neumann architecture computer, in which both instructions and data are stored in the same memory system and (without the complexity of a CPU cache) must be accessed in turn.
The physical separation of instruction and data memory is sometimes held to be the distinguishing feature of modern Harvard architecture computers.
A computer with a von Neumann architecture has the advantage over Harvard machines as described above in that code can also be accessed and treated the same as data, and vice versa.
This is the point of pure or modified Harvard machines, and why they co-exist with the more flexible and general von Neumann architecture: separate memory pathways to the CPU allow instructions to be fetched and data to be accessed at the same time, improving throughput.
From a programmer's point of view, a modified Harvard processor in which instruction and data memories share an address space is usually treated as a von Neumann machine until cache coherency becomes an issue, as with self-modifying code and program loading.
The original Harvard machine, the Mark I, stored instructions on a punched paper tape and data in electro-mechanical counters.
In contrast, a von Neumann microcontroller such as an ARM7TDMI, or a modified Harvard ARM9 core, necessarily provides uniform access to flash memory and SRAM (as 8 bit bytes, in those cases).
Outside of applications where a cacheless DSP or microcontroller is required, most modern processors have a CPU cache which partitions instruction and data.
Similar solutions are found in other microcontrollers such as the PIC and Z8Encore!, many families of digital signal processors such as the TI C55x cores, and more.