OVPsim is a multiprocessor platform emulator (often called a full-system simulator) used to run unchanged production binaries of the target hardware.
Various processor, peripheral and platform models are available as free software under the Apache License version 2.0.
These components are designed to make it easy to assemble multi-core heterogeneous or homogeneous platforms with complex memory hierarchies, cache systems and layers of embedded software that can run at hundreds of MIPS on standard desktop PCs.
There are many examples of components, and complete virtual platforms that can boot a Linux kernel in under 5 seconds at OVP homepage.
Currently there are processor models of ARM (processors using the ARMv4, ARMv5, ARMv6, ARMv7, ARMv8 instruction sets) up to the ARM Cortex-A72MPx4 (and including multi-cluster ARMv8 models with GICv3), Imagination MIPS (processors using MIPS32, MIPS64, microMIPS, nanoMIPS and MIPS R6 instruction sets) up to the microAptiv, interAptiv, proAptiv, and Warrior cores, Synopsys Virage ARC600/ARC700 and ARC EM series, Renesas v850, RH850, RL78 and m16c, PowerPC, Altera Nios II, Xilinx MicroBlaze, RISC-V (models using 32bit RV32I, RV32M, RV32IM, RV32A, RV32IMA, RV32IMAC, RV32F, RV32D, RV32E, RV32EC, RV32C, RV32G, RV32GC, RV32GCN, RV32IMAFD and 64bit RV64I, RV64M, RV64IMAC, RV64F, RV64D, RV64C, RV64G, RV64GC, RV64GCN, RV64IMAFD ISA subsets), Andes Technology N25/NX25, N25F/NX25F, A25/AX25, A25F/AX25F, Microsemi CoreRISCV/MiV-RV32IMA, SiFive E31, E51, U54, U54-MC, Freedom U540, Codasip Series 1, 3, 5, 7 RISC-V cores, Intel NiosV RISC-V core, Texas Instruments TMS320 DSP, and OpenRisc families.
Several different pre-built platforms are available, including the most common operating systems[4] ucLinux, Linux, Android, FreeRTOS, Nucleus, Micrium.
OVPsim comes with the Imperas iGui Graphical Debugger and also an Eclipse IDE and CDT interface.
OVPsim can be encapsulated and called from within other simulation environments[5] and comes as standard with interface files for C, C++, and SystemC.
There is an interception mechanism enabling emulation of calls to functions in the application runtime libraries (such as write, fstat etc.)
[citation needed] It is also leveraged for educational courses to allow students to develop and debug application software and create virtual platforms and new models.
The technology was licensed by MIPS[11] Technologies to provide modeling support for their MIPS architecture embedded processor range, features in a partnership with leading processor provider ARM,[12][13] and is part of the Europractice[14] product range for general access to European universities.
A version of OVPsim is used by the RISC-V Foundation's Compliance Working Group[15] as a reference simulator.