Operand forwarding (or data forwarding) is an optimization in pipelined CPUs to limit performance deficits which occur due to pipeline stalls.
[1][2] A data hazard can lead to a pipeline stall when the current operation has to wait for the results of an earlier operation which has not yet finished.
If these two assembly pseudocode instructions run in a pipeline, after fetching and decoding the second instruction, the pipeline stalls, waiting until the result of the addition is written and read.
In some cases all stalls from such read-after-write data hazards can be completely eliminated by operand forwarding:[3][4][5] The CPU control unit must implement logic to detect dependencies where operand forwarding makes sense.
A multiplexer can then be used to select the proper register or flip-flop to read the operand from.