POWER7 is a family of superscalar multi-core microprocessors based on the Power ISA 2.06 instruction set architecture released in 2010 that succeeded the POWER6 and POWER6+.

[2][3] IBM won a $244 million DARPA contract in November 2006 to develop a petascale supercomputer architecture before the end of 2010 in the HPCS project.

[4] One feature that IBM and DARPA collaborated on is modifying the addressing and page table hardware to support global shared memory space for POWER7 clusters.

From a productivity standpoint, this is essential since some scientists are not conversant with MPI or other parallel programming techniques used in clusters.

[5] The POWER7 superscalar multi-core architecture was a substantial evolution from the POWER6 design, focusing more on power efficiency through multiple cores and simultaneous multithreading (SMT).

[7] IBM stated at ISCA 29[8] that peak performance was achieved by high frequency designs with 10–20 FO4 delays per pipeline stage at the cost of power efficiency.

For example, in the Supercomputing (HPC) System Power 775 it is packaged as a 32-way quad-chip-module (QCM) with 256 physical cores and 1024 SMTs.

"[11] The new IBM Power 780 scalable, high-end servers featuring the new TurboCore workload optimizing mode and delivering up to double performance per core of POWER6 based systems.

[16] At 3.4 GHz (i7-4770) this translates into 108.8 SP GFLOPS per core and 435.2 SP GFLOPS peak performance across the 4-core chip, giving roughly similar levels of performance per core, without taking into account the effects or benefits of Intel's Turbo Boost technology.

This theoretical peak performance comparison holds in practice too, with the POWER7 and the i7-4770 obtaining similar scores in the SPEC CPU2006 floating point benchmarks (single-threaded): 71.5[17] for POWER7 versus 74.0[18] for i7-4770.