It is claimed to be part of the eCLipz project, said to have a goal of converging IBM's server hardware where practical (hence "ipz" in the acronym: iSeries, pSeries, and zSeries).

The binary floating-point unit incorporates "many microarchitectures, logic, circuit, latch and integration techniques to achieve [a] 6-cycle, 13-FO4 pipeline", according to a company paper.

[8] Each core has a 64 KB, four-way set-associative instruction cache and a 64 KB data cache of an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle.

[10] POWER6 can connect to up to 31 other processors using two inter node links (50 GB/s), and supports up to 10 logical partitions per core (up to a limit of 254 per system).

There is an interface to a service processor that monitors and adjusts performance and power according to set parameters.

[11] IBM also makes use of a 5 GHz duty-cycle correction clock distribution network for the processor.

[12] The slightly enhanced POWER6+ was introduced in April 2009, but had been shipping in Power 560 and 570 systems since October 2008.

The main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand (CUoD) capabilities and hot-pluggable processor and memory "books".