[1] In a standard five-stage pipeline, during the decoding stage, the control unit will determine whether the decoded instruction reads from a register to which the currently executed instruction writes.
If this condition holds, the control unit will stall the instruction by one clock cycle.
The values are preserved until the instruction causing the conflict has passed through the execution stage.
In some architectures, the execution stage of the pipeline must always be performing an action at every cycle.
The below example shows a bubble being inserted into a classic RISC pipeline, with five stages (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back).