Power ISA
It has multiple sets of registers: Instructions up to version 3.0 have a length of 32 bits, with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications, and version 3.1 which introduced prefixing to create 64-bit instructions.
The sprawl of instructions and technologies has made the complete specification unwieldy, so the OpenPOWER Foundation have decided to enabled tiered compliancy.
It is however recommended that an option be provided to disable any added functions beyond the design's declared subset level.
A design must be compliant at its declared subset level to make use of the Foundation's protection regarding use of intellectual property, be it patents or trademarks.
At present this leaves new OpenPOWER implementors wishing to run standard Linux distributions having to implement a massive 962 instructions.
The Book I included five new chapters regarding auxiliary processing units like DSPs and the AltiVec extension.
[14] Book III-E also includes significant enhancement for the embedded specification regarding hypervisor and virtualisation on single and multi core implementations.
It is based on Power ISA v.2.06 and includes major enhancements to logical partition functions, transactional memory, expanded performance monitoring, new storage control features, additions to the VMX and VSX vector facilities (VSX-2), along with AES[16]: 257 [17] and Galois Counter Mode (GCM), SHA-224, SHA-256,[16]: 258 SHA-384 and SHA-512[16]: 258 (SHA-2) cryptographic extensions and cyclic redundancy check (CRC) algorithms.
It is the first to come out after the founding of the OpenPOWER Foundation and includes enhancements for a broad spectrum of workloads and removes the server and embedded categories while retaining backwards compatibility and adds support for VSX-3 instructions.
New functions include 128-bit quad-precision floating-point operations, a random number generator, hardware-assisted garbage collection and hardware-enforced trusted computing.
Mainly giving support for new functions introduced in Power10, but also includes the notion of optionality to the PowerISA specification.
VSX and the SVP64 extension provide hardware support for 16-bit half precision floats.
