The fetching of opcodes well in advance, prior to their need for execution, increases the overall efficiency of the processor boosting its speed.
The processor no longer has to wait for the memory access operations for the subsequent instruction opcode to complete.
Pipelining is the broader concept and most modern processors load their instructions some clock cycles before they execute them.
This is achieved by pre-loading machine code from memory into a prefetch input queue.
If the PIQ is not flushed, the processor might translate its codes wrong and generate an invalid instruction exception.
It simply executes its old copy already loaded in the PIQ instead of the new and altered version of the code in its RAM and/or cache.
This behavior of the PIQ can be used to determine if code is being executed inside an emulator or directly on the hardware of a real CPU.
Different queueing models are proposed in order to approximately simulate the real time queuing systems so that those can be analysed mathematically for different performance specifications.
In this case, the entire queue must be dumped and the contents pointed to by the instruction pointer must be fetched from memory.
Processors implementing the instruction queue prefetch algorithm are rather technically advanced.