Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly.
[1] To verify the robustness of an integrated circuit design, semiconductor manufacturers will fabricate corner lots, which are groups of wafers that have had process parameters adjusted according to these extremes, and will then test the devices made from these special wafers at varying increments of environmental conditions, such as voltage, clock frequency, and temperature, applied in combination (two or sometimes all three together) in a process called characterization.
This variation can cause significant changes in the duty cycle and slew rate of digital signals, and can sometimes result in catastrophic failure of the entire system.
Then the corners cbest and cworst were created to model the smallest and largest cross sections that are in the allowed process variation.
But the one change is that cross sectional resistance is not dependent on oxide thickness (vertical spacing between wires) so for rcbest the largest is used and for rcworst the smallest is used.
To combat these variation effects, modern technology processes often supply SPICE or BSIM simulation models for all (or, at the least, TT, FS, and SF) process corners, which enables circuit designers to detect corner skew effects before the design is laid out, as well as post-layout (through parasitics extraction), before it is taped out.