Reduced instruction set computer
[1] The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register).
The conceptual developments of the RISC computer architecture began with the IBM 801 project in the late 1970s, but these were not immediately put into use.
The varieties of RISC processor design include the ARC processor, the DEC Alpha, the AMD Am29000, the ARM architecture, the Atmel AVR, Blackfin, Intel i860, Intel i960, LoongArch, Motorola 88000, the MIPS architecture, PA-RISC, Power ISA, RISC-V, SuperH, and SPARC.
[13] The telephone switch program was canceled in 1975, but by then the team had demonstrated that the same design would offer significant performance gains running just about any code.
In simulations, they showed that a compiler tuned to use registers wherever possible would run code about three times as fast as traditional designs.
In practice, their experimental PL/8 compiler, a slightly cut-down version of PL/I, consistently produced code that ran much faster on their existing mainframes.
[13] A 32-bit version of the 801 was eventually produced in a single-chip form as the IBM ROMP in 1981, which stood for 'Research OPD [Office Products Division] Micro Processor'.
[19] In 1979, David Patterson was sent on a sabbatical from the University of California, Berkeley to help DEC's west-coast team improve the VAX microcode.
The Program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics.
[21] Patterson's early work pointed out an important problem with the traditional "more is better" approach; even those instructions that were critical to overall performance were being delayed by their trip through the microcode.
[21] In the original RISC-I paper they noted:[22] Skipping this extra level of interpretation appears to enhance performance while reducing chip size.
This led the Berkeley design to select a method known as register windows which can significantly improve subroutine performance although at the cost of some complexity.
[22] They also noticed that the majority of mathematical instructions were simple assignments; only 1⁄3 of them actually performed an operation like addition or subtraction.
This led to far more emphasis on the underlying arithmetic data unit, as opposed to previous designs where the majority of the chip was dedicated to control and microcode.
This MIPS project grew out of a graduate course by John L. Hennessy, produced a functioning system in 1983, and could run simple programs by 1984.
[27]Competition between RISC and conventional CISC approaches was also the subject of theoretical analysis in the early 1980s, leading, for example, to the iron law of processor performance.
[16][30] The US government Committee on Innovations in Computing and Communications credits the acceptance of the viability of the RISC concept to the success of the SPARC system.
[16] By 1989 many RISC CPUs were available; competition lowered their price to $10 per MIPS in large quantities, much less expensive than the sole sourced Intel 80386.
[citation needed] The ARM architecture has been the most widely adopted RISC ISA, initially intended to deliver higher-performance desktop computing, at low cost, and in a restricted thermal package, such as in the Acorn Archimedes, while featuring in the Super Computer League tables, its initial, relatively, lower power and cooling implementation was soon adapted to embedded applications, such as laser printer raster image processing.
[32] Acorn, in partnership with Apple Inc, and VLSI, creating ARM Ltd, in 1990, to share R&D costs and find new markets for the ISA, who in partnership with TI, GEC, Sharp, Nokia, Oracle and Digital would develop low-power and embedded RISC designs, and target those market segments, which at the time were niche.
In a CISC processor, the hardware may internally use registers and flag bit in order to implement a single complex instruction such as STRING MOVE, but hide those details from the compiler.
[40][41] Most RISC architectures have fixed-length instructions and a simple encoding, which simplifies fetch, decode, and issue logic considerably.
[43] One drawback of 32-bit instructions is reduced code density, which is more adverse a characteristic in embedded computing than it is in the workstation and server markets RISC architectures were originally designed to serve.
To address this problem, several architectures, such as SuperH (1992), ARM thumb (1994),[44] MIPS16e (2004), Power Variable Length Encoding ISA (2006), RISC-V, and the Adapteva Epiphany, have an optional short, feature-reduced compressed instruction set.
[citation needed] Some aspects attributed to the first RISC-labeled designs around 1975 include the observations that the memory-restricted compilers of the time were often unable to take advantage of features intended to facilitate manual assembly coding, and that complex addressing modes take many cycles to perform due to the required additional memory accesses.
that such functions would be better performed by sequences of simpler instructions if this could yield implementations small enough to leave room for many registers, reducing the number of slow memory accesses.
The goal was to make instructions so simple that they could easily be pipelined, in order to achieve a single clock throughput at high frequencies.
[47] Later, it was noted that one of the most significant characteristics of RISC processors was that external memory was only accessible by a load or store instruction.
[56] Outside of the desktop arena, however, the ARM RISC architecture is in widespread use in smartphones, tablets and many forms of embedded devices.
Examples include: In 2022 Steve Furber, John L. Hennessy, David A. Patterson and Sophie M. Wilson were awarded the Charles Stark Draper Prize by the United States National Academy of Engineering for their contributions to the invention, development, and implementation of reduced instruction set computer (RISC) chips.
