[1][2] Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s.

SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992.

Later, SPARC processors were used in symmetric multiprocessing (SMP) and non-uniform memory access (CC-NUMA) servers produced by Sun, Solbourne, and Fujitsu, among others.

The design was turned over to the SPARC International trade group in 1989, and since then its architecture has been developed by its members.

Much of the processor core development group in Austin, Texas, was dismissed, as were the teams in Santa Clara, California, and Burlington, Massachusetts.

[4][5] Fujitsu will also discontinue their SPARC production (has already shifted to producing their own ARM-based CPUs), after two "enhanced" versions of Fujitsu's older SPARC M12 server in 2020–22 (formerly planned for 2021) and again in 2026–27, end-of-sale in 2029, of UNIX servers and a year later for their mainframe and end-of-support in 2034 "to promote customer modernization".

This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide.

Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

According to the "Oracle SPARC Architecture 2015" specification an "implementation may contain from 72 to 640 general-purpose 64-bit" registers.

This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load–store) level or at the memory page level (via an MMU setting).

It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Philips, Ross Technology, Sun Microsystems, and Texas Instruments.

In 2002, the SPARC Joint Programming Specification 1 (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality").

In December 2007, Sun also made the UltraSPARC T2 processor's RTL available via the OpenSPARC project.

[7][15] This revision includes VIS 4 instruction set extensions and hardware-assisted encryption and silicon secured memory (SSM).

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks.

The LDF, LDDF, and LDQF instructions load a single-precision, double-precision, or quad-precision value from memory into a floating-point register; the STF, STDF, and STQF instructions store a single-precision, double-precision, or quad-precision floating-point register into memory.

[19] Arithmetic and logical instructions also use a three-operand format, with the first two being the operands and the last being the location to store the result.

Examples include:[18] The list of mathematical instructions is ADD, SUB, AND, OR, XOR, and negated versions ANDN, ORN, and XNOR.

If one wants the condition codes to be set, this is indicated by adding cc to the instruction:[18] add and sub also have another modifier, X, which indicates whether the operation should set the carry bit: SPARC V7 does not have multiplication or division instructions, but it does have MULSCC, which does one step of a multiplication testing one bit and conditionally adding the multiplicand to the product.

SPARC V8 added UMUL (unsigned multiply), SMUL (signed multiply), UDIV (unsigned divide), and SDIV (signed divide) instructions, with both versions that do not update the condition codes and versions that do.

The 22-bit displacement field is the address, relative to the current PC, of the target, in words, so that conditional branches can go forward or backward up to 8 megabytes.

To make this even easier, the assembler also includes a "synthetic instruction", set, that performs these two operations in a single line: This outputs the two instructions above if the value is larger than 13 bits, otherwise it will emit a single ld with the value.

[18] As noted earlier, the SPARC assembler uses "synthetic instructions" to ease common coding tasks.

Additional examples include (among others):[18] Intel was the 80386's only producer, which made it very expensive and caused the industry to be wary of sole sourced CPUs.

[20] The following organizations have licensed the SPARC architecture: Matsushita[21] Notes: SPARC machines have generally used Sun's SunOS, Solaris, JavaOS, or OpenSolaris including derivatives illumos and OpenIndiana, but other operating systems have also been used, such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux.

In 1993, Intergraph announced a port of Windows NT to the SPARC architecture,[47] but it was later cancelled.

[48] Several fully open source implementations of the SPARC architecture exist: A fully open source simulator for the SPARC architecture also exists: For HPC loads Fujitsu builds specialized SPARC64 fx processors with a new instruction extensions set, called HPC-ACE (High Performance Computing – Arithmetic Computational Extensions).

[52] Newer HPC processors, IXfx and XIfx, were included in recent PRIMEHPC FX10 and FX100 supercomputers.

1 as of November 2014[53]) has a number of nodes with Galaxy FT-1500 OpenSPARC-based processors developed in China.