TeraScale (microarchitecture)
TeraScale was also used in the AMD Accelerated Processing Units code-named "Brazos", "Llano", "Trinity" and "Richland".
[6] At FOSDEM09 Matthias Hopf from AMDs technology partner SUSE Linux presented a slide regarding the programming of open-source driver for the R600.
[8] The new unified shader functionality is based upon a very long instruction word (VLIW) architecture in which the core executes operations in parallel.
Each stream processing unit can retire a finished single precision floating point MAD (or ADD or MUL) instruction per clock, dot product (DP, and special cased by combining ALUs), and integer ADD.
[10] The 5th unit is more complex and can additionally handle special transcendental functions such as sine and cosine.
TeraScale 1 based GPU's (HD 2000, 3000 and 4000 series) are only conformant to Direct3D 10 and OpenGL 3.3 and implements therefore a different tessellation principle which uses vendor specific API extensions.
[11] The TeraScale 2 based GPU's (starting with the Radeon HD 5000 series) were the first to conform with both Direct3D 11 and OpenGL 4.0 tesselation technique.
[13] The TeraScale tessellator units allow the developers to take a simple polygon mesh and subdivide it using a curved surface evaluation function.
[14] Essentially, this allows a simple, low-polygon model to be increased dramatically in polygon density in real-time with very small impact on the performance.
Scott Wasson of Tech Report noted during an AMD demo that the resulting model was so dense with millions of polygons that it appeared to be solid.
A few games (such as Madden NFL 2004, Serious Sam, Unreal Tournament 2003 and 2004, and unofficially Morrowind), had the support for the ATI's tesselation technology included.
Such a slow adaptation has to do with the fact that it was not a feature shared with NVIDIA GPUs, since those had implemented a competing tessellation solution using Quintic-RT patches which had achieved even less support from the major game developers.
This processor manages a large number of in-flight threads of three distinct types (vertex, geometry, and pixel shaders) and switches amongst them as needed.
[9] The render output units (ROPs) of Radeon HD 2000 series now performs the task of Multisample anti-aliasing (MSAA) with programmable sample grids and maximum of 8 sample points, instead of using pixel shaders as in the Radeon X1000 series.
[21] ) (see list of chips in those pages) TeraScale 2 (VLIW5) was introduced with Radeon HD 5000 series GPUs in "Evergreen" generation.
The architecture of stream cores is largely unchanged, but adds support for DirectX 11/DirectCompute 11 capabilities with new instructions.
TeraScale 3 is introduced in the Radeon HD 6900-branded graphics cards and also implemented in the Trinity and Richland APUs.
AMD PowerTune, dynamic frequency scaling for GPUs, was introduced with the Radeon HD 6900 series on December 15, 2010 and has seen continued development, as documented in some reviews by AnandTech.
