Digital timing diagram

SPI operates in the following way: When a slave's SS line is high, both its MISO and MOSI line should be high impedance to avoid disrupting a transfer to a different slave.

Before SS being pulled low, the MISO & MOSI lines are indicated with a "z" for high impedance.

Also, before the SS is pulled low, the "cycle #" row is meaningless and is shown greyed out.

Note that for CPHA=1, the MISO & MOSI lines are undefined until after the first clock edge and are also shown greyed out before that.

A more typical timing diagram has just a single clock and numerous data lines.