Brent–Kung adder

Proposed by Richard Peirce Brent and Hsiang Te Kung in 1982 it introduced higher regularity to the adder structure and has less wiring congestion leading to better performance and less necessary chip area to implement compared to the Kogge–Stone adder (KSA).

The time taken for addition was directly proportional to the length of the bit being added.

This is reverse in Brent–Kung adders where the carry is calculated in parallel thus reducing the addition time drastically.

thus making it a good-choice adder with constraints on area and maximizing the performance.

Its symmetry and regular build structure reduces costs of production effectively and enable it to be used in pipeline architectures.

Taking advantage of the associativity of operator ○, (Gn, Pn) can be computed in a tree-like manner.

The increase in performance in Brent–Kung adders is attributed to its tree structure of carry propagation which also leads to lower power consumption as the carry signal now has to travel through fewer stages, leading to less switching of transistors.

Also, the decrease in amount of wiring and fan-out also contributes largely to its lower power consumption than CLA adders.

[3] This type of adder has greater delay,[3] requiring 2 log2 n − 2 levels of logic to compute all the carry bits.