Carry-skip adder
Unlike other fast adders, carry-skip adder performance is increased with only some of the combinations of input bits.
This means, speed improvement is only probabilistic.
The worst case for a simple one level ripple-carry adder occurs, when the propagate-condition[1] is true for each digit pair
For each operand input bit pair
When all propagate-conditions are true, then the carry-in bit
The n-bit-carry-skip adder consists of a n-bit-carry-ripple-chain, a n-input AND-gate and one multiplexer.
, that is provided by the carry-ripple-chain is connected to the n-input AND-gate.
This greatly reduces the latency of the adder through its critical path, since the carry bit for each block can now "skip" over blocks with a group propagate signal set to logic 1 (as opposed to a long ripple-carry chain, which would require the carry to ripple through each bit in the adder).
The number of inputs of the AND-gate is equal to the width of the adder.
For a large width, this becomes impractical and leads to additional delays, because the AND-gate has to be built as a tree.
A good width is achieved, when the sum-logic has the same depth like the n-input AND-gate and the multiplexer.
The critical path of a carry-skip-adder begins at the first full-adder, passes through all adders and ends at the sum-bit
Carry-skip-adders are chained (see block-carry-skip-adders) to reduce the overall critical path, since a single
-bit carry-skip-adder has no real speed benefit compared to a
As the propagate signals are computed in parallel and are early available, the critical path for the skip logic in a carry-skip adder consists only of the delay imposed by the multiplexer (conditional skip).
There are two types of block-carry-skip adders The two operands
Fixed size block-carry-skip adders split the
The critical path consists of the ripple path and the skip element of the first block, the skip paths that are enclosed between the first and the last block, and finally the ripple-path of the last block.
The optimal block size for a given adder width n is derived by equating to 0 Only positive block sizes are realizable The performance can be improved, i.e. all carries propagated more quickly by varying the block sizes.
Accordingly the initial blocks of the adder are made smaller so as to quickly detect carry generates that must be propagated the furthers, the middle blocks are made larger because they are not the problem case, and then the most significant blocks are again made smaller so that the late arriving carry inputs can be processed quickly.
are further summarized and used to perform larger skips: Thus making the adder even faster.
The problem of determining the block sizes and number of levels required to make the physically fastest carry-skip adder is known as the 'carry-skip adder optimization problem'.
This problem is made complex by the fact that a carry-skip adders are implemented with physical devices whose size and other parameters also affects addition time.
The carry-skip optimization problem for variable block sizes and multiple levels for an arbitrary device process node was solved by Oklobdzija and Barnes at IBM and published in 1985.
Breaking this down into more specific terms, in order to build a 4-bit carry-bypass adder, 6 full adders would be needed.
The input buses would be a 4-bit A and a 4-bit B, with a carry-in (CIN) signal.
The output would be a 4-bit bus X and a carry-out signal (COUT).
The second set of 2 full adders would add the last two bits assuming
And the final set of full adders would assume that
The multiplexers then control which output signal is used for COUT,
