The carry-select adder is simple but rather fast, having a gate level depth of
The number of bits in each carry select block can be uniform, or variable.
The optimal delay occurs when variable size of the blocks is applied[1]
When variable, the block size should have a delay, from addition inputs A and B to the carry out, equal to that of the multiplexer chain leading into it, so that the carry out is calculated just in time.
delay is derived from uniform sizing, where the ideal number of full-adder elements per block is equal to the square root of the number of bits being added, since that will yield an equal number of MUX delays.
Two 4-bit ripple-carry adders are multiplexed together, where the resulting carry and sum bits are selected by the carry-in.
Since carry-in is known at the beginning of computation, a carry select block is not needed for the first four bits.
A 16-bit carry-select adder with variable size can be similarly created.
Here we show an adder with block sizes of 2-2-3-4-5, this is the special type of Variable-sized carry select adder, called as square root carry select adder.
In the conditional sum adder, the MUX level chooses between two n/2-bit inputs that are themselves built as conditional-sum adder.
The conditional sum adder suffers from a very large fan-out of the intermediate carry outputs.
The carry-select adder design can be complemented with a carry-lookahead adder structure to generate the MUX inputs, thus gaining even greater performance as a parallel prefix adder while potentially reducing area.