Dennard scaling

[1][2] The law, originally formulated for MOSFETs, is based on a 1974 paper co-authored by Robert H. Dennard, after whom it is named.

, and the off-current grows exponentially with the field, resulting in high static power consumption since the 90 nm node.

Dennard's model of MOSFET scaling implies that, with every technology generation: Moore's law says that the number of transistors on a microchip doubles approximately every two years.

Combined with Dennard scaling, this means that performance per joule grows even faster, doubling about every 18 months (1.5 years).

[7] The dynamic (switching) power consumption of CMOS circuits is proportional to frequency.

[8] Historically, the transistor power reduction afforded by Dennard scaling allowed manufacturers to drastically raise clock frequencies from one generation to the next without significantly increasing overall circuit power consumption.

This is the "power wall", which caused Intel to cancel Tejas and Jayhawk in 2004.

[1][10] The primary reason cited for the breakdown is that at small sizes, current leakage poses greater challenges and also causes the chip to heat up, which creates a threat of thermal runaway and therefore further increases energy costs.

[1][10] Since 2005, the clock frequency has stagnated at 4 GHz, and the power consumption per CPU at 100 W TDP.

The breakdown of Dennard scaling and resulting inability to increase clock frequencies significantly has caused most CPU manufacturers to focus on multicore processors as an alternative way to improve performance.

An increased core count benefits many (though by no means all – see Amdahl's law) workloads, but the increase in active switching elements from having multiple cores still results in increased overall power consumption and thus worsens CPU power dissipation issues.

[11][12] The end result is that only some fraction of an integrated circuit can actually be active at any given point in time without violating power constraints.